Large, complex, integrated circuits (“ICs”) incorporate millions of circuit elements, such as memory cells and transistors. Many of the transistors are typically used in switching circuits, connecting a data source to a data destination. One type of switch is commonly called a “flip-flop” or simply a “flop”. It is generally desirable to operate the flops as fast as possible; however, several limitations can arise.
On physically large ICs, such as field-programmable gate arrays (“FPGAs”), data skew can occur between a flip-flop at one location on the IC and a flip-flop at another location. In a synchronous system, the data arriving at the two different flip-flops typically has to remain valid for each flop during a short portion of the clock cycle. The time allowed for all flip-flops in a clock domain to receive valid data during a clock cycle is called the “timing margin”. Longer timing margins generally correspond to slower IC operation.
Many FPGAs and complex programmable logic devices (“CPLDs”) employ techniques for reducing clock skew and flip-flop delay in order to achieve higher operating speeds. As a result, many flip-flops in a synchronous design switch almost simultaneously. This creates an impulse event (“spike”) in the current drawn from an on-chip voltage supply, such as VCC. The current spikes arising from a switching event cause fluctuations of the supply voltage, commonly called supply noise. Noise on a voltage supply typically increases the jitter on clock and data paths, eroding timing margins required for reliable circuit operation.
Techniques for reducing supply noise are desirable because less noise leads to reduced jitter, which improves timing margin, enhancing system robustness and enabling operation at higher clock frequencies.